Rapidly growing technologies such as data analytics, database technology, and cloud services demand low-latency, non-volatile solution to hold vast amounts of data. Flash storage devices, such as solid-state drives (SSDs) are widely used in data center environments. SSD technology often includes interfaces compatible with traditional block input/output (I/O) hard disk drives. As opposed to traditional electromechanical magnetic storage, SSDs generally have no moving mechanical components. Therefore, SSDs are typically more resistant to physical shock, provide lower access time and lower latency, and run without generating detectable noise.
Currently, many SSDs use dynamic random-access memory (DRAM) to implement caches for holding data and instructions, where a loss of power can lead to a permanent loss of data. DRAM may be used as the write cache to receive the user data so that when the user data is held in DRAM, the SSD can acknowledge to the host that the current write operation has completed successfully, and then physically writes the data into NAND flash. This mechanism is known as “write-back”.
To accelerate programming and read operations, NAND flash devices have included internal DRAM used as both a read cache and a write cache. By configuring the cache using write-back instead of write-though, when data resides in DRAM, flash devices acknowledge to the host that the current data has been safely written. In this way, the write latency is greatly reduced from hundreds of microseconds to tens of microseconds, and the main cause of latency results on the transfer path. For the read cache, depending on the hit rate, data acquisition is accelerated and comprises shorter average latency. However, there is difficulty in enforcing the data integrity of the internal DRAM cache, and it is extremely challenging for NAND flash devices with large cache content. The current strategy to enforce the data integrity is an additional backup battery unit (BBU) for flash devices. When a power failure occurs, the BBU provides sufficient power to write the data from DRAM to NAND flash for permanent storage.
There are several drawbacks to using a BBU. For example, when the battery is being charged, other device modules cannot receive maximum power. Furthermore, the use of a DRAM-based architecture can also lead to long wait time at power up, high power consumption, high total cost of ownership (TCO), and suboptimal usage of NAND flash, for example. Therefore, there is a strong desire to avoid the use of DRAM-based caches and BBUs on single devices, such as Peripheral Component Interconnect Express (PCIe) SSDs, host bus adapter (HBA) cards, etc. What is needed is a flash storage device that combines the power loss protection features of BBUs without the added cost and complexity inherent in battery units.